A semiconductor nanowire refers to a semiconductor wire having transverse lateral and vertical dimensions of the order of a nanometer (10−9 meter) or tens of nanometers. Typically, the transverse lateral dimension and the vertical dimension are less than 20 nm.
The limitation on the lateral dimension applies to the transverse lateral dimension (the width) and the vertical lateral dimension (the height). The longitudinal lateral dimension (the length) of the semiconductor nanowire is unlimited, and may be, for example, from 1 nm to 1 mm. When the lateral dimensions of the semiconductor nanowire is less than ten nanometers, quantum mechanical effects may become important.
A semiconductor nanowire enables enhanced control of the charge carriers along the lengthwise direction through a complete encirclement of the cross-sectional area of the semiconductor nanowire by a gate dielectric and a gate electrode. The charge transport along the semiconductor nanowire by the gate electrode is better controlled in a semiconductor nanowire device than in a fin field effect transistor (finFET) because of the complete encirclement of the semiconductor nanowire.
The transverse lateral dimension of a semiconductor nanowire is currently sublithographic, i.e., may not be printed by a direct image transfer from a photoresist that is patterned by a single exposure. As of 2008, the critical dimension, i.e., the smallest printable dimension that may be printed by lithographic methods, is about 35 nm. Dimensions less than the critical dimension are called sublithographic dimensions. At any given time, the critical dimension and the range of the sublithographic dimension are defined by the best available lithographic tool in the semiconductor industry. In general, the critical dimension and the range of the sublithographic dimension decreases in each successive technology node and established by a manufacturing standard accepted across the semiconductor industry.
To enable the transverse lateral dimension for a semiconductor nanowire, a thinning process is typically employed in which a semiconductor link portion formed by lithographic methods and having a lithographic transverse dimension is reduced in size by conversion of the outer portions of the semiconductor link portion. For example, a thermal oxidation of the semiconductor material constituting the semiconductor link portion may be employed to form a semiconductor nanowire having a sublithographic transverse lateral dimension.
Such thinning process generates significant level of stress and oftentimes results in structural breakdown of a semiconductor nanowire. However, structural stability of the semiconductor nanowire to form semiconductor nanowire devices with high yield.